`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:52:31 10/22/2012 
// Design Name: 
// Module Name:    CPLX_MUL_UNIT 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module CPLX_MUL_UNIT #(parameter WIDTH = 16)
(	
	 input clk,
	 input rst,
    input signed [WIDTH-1:0] a_r,
    input signed [WIDTH-1:0] a_i,
    input signed [WIDTH-1:0] b_r,
    input signed [WIDTH-1:0] b_i,
    output reg signed[WIDTH+WIDTH+1-1:0] out_r,
    output reg signed[WIDTH+WIDTH+1-1:0] out_i

    );
	 

	always@(posedge clk or negedge rst)
		if(!rst)
		begin
			out_r <= 0;
			out_i <= 0;
		end
		else
		begin
			out_r <= a_r*b_r-a_i*b_i;
			out_i <= a_r*b_i+a_i*b_r;
		end

endmodule
